The present invention relates to a secondary storage apparatus in a computer system and more particularly to a disk storage system having high input/output data transfer performance.
In a current computer system, data required by a CPU (Central Processing Unit) are stored in a secondary storage apparatus and data are written in and read out from the secondary storage apparatus when the CPU or the like requires the data.
As the secondary storage apparatus, a non-volatile memory medium is generally used and as its representative, there is a disk storage system such as a magnetic disk apparatus and an optical disk.
With the high advancement of the information-oriented society in recent years, high-performance of the secondary storage apparatus of this kind is required in the computer system.
FIG. 9 is a block diagram schematically illustrating a conventional disk storage system.
In FIG. 9, the disk storage system includes a disk controller DKC and a disk array DA.
The disk controller DKC includes a channel adapter CHA for connecting the disk storage system to a higher-rank CPU (not shown), a cache memory CM for temporarily storing data written in and read out from the disk array DA and a disk adapter DKA for connecting the disk controller DKC to the disk array DA.
The channel adapter CHA, the cache memory CM and the disk adapter DKA are connected through a bus or switch.
The channel adapter CHA includes four channels C1, C2, C3 and C4 connected to the CPU.
The disk adapter DKA is connected to the disk array through four channels D1, D2, D3 and D4.
The disk array DA includes disk groups R1, R2, R3 and R4.
When the RAID system is constructed in the disk array DA, the disk groups R1, R2, R3 and R4 each constitute RAID groups.
Write data inputted from the channels C1, C2, C3 and C4 are stored in the cache memory CM and at the same time the write data are divided into data of block-size unit, so that the data divided in the block unit are sent through three channels of the channels D1, D2, D3 and D4 and a parity calculated from the divided data is sent through a remaining channel from the disk adapter DKA to the disk array DA.
When data is read out, it is first examined whether the data is present or stored in the cache memory CM.
When the data is present in the cache memory CM, the data is read out through the channel adapter CHA from the cache memory CM and transmitted through the channel adapter CHA to the CPU.
When the data is not present in the cache memory CM, the disk adapter DKA reads out the data divided in the block unit from the disk array DA through the channels D1, D2, D3 and D4 and transmits the read data through the channel adapter CHA to the CPU. The conventional technique of this kind is named the first conventional technique.
The disk storage system related to the first conventional technique is described in, for example, “MAIN FRAME in Separate Volume of Nikkei Computer '98”, pp. 144 to 153 issued by Nikkei BP Co. (1998).
A disk storage system having a disk array connected to a disk adapter through switches is disclosed in JP-A-5-173722 entitled “Exchange Device of Multi-Channel Data and Parity”.
The conventional technique described in the above publication is hereinafter named the second conventional technique.
According to the second conventional technique, the number of buses related to the disk array and the number of buses related to the disk adapter can be set up independently.
A disk storage system having a disk array connected to a disk adapter through a buffer control block is disclosed in JP-A-6-19627 entitled “Rotation Type Storage Apparatus”.
The conventional technique described in the above publication is hereinafter named the third conventional technique.
According to the third conventional technique, a data transfer rate between the disk adapter and the disk array can be set up to any value and influence due to a waiting time caused by rotation of the disk can be reduced.
The date transfer rate per channel is increased year after year with the progress of network technique.
For example, the data transfer rate per channel in a fiber channel used in a disk storage system is 1 to 2 Gbps at present but is planned to be increased to 4 to 10 Gbps in the near future.
It is forecasted that the throughput between the CPU and the channel adapter (hereinafter named the front-end) complies with the above increased data transfer rate.
However, it is forecasted that the throughput between the disk adapter and the disk array (hereinafter named the back-end) is not increased as the front-end due to the following reasons.
The first reason is that the disk drive contains mechanical components and accordingly the high-speed operation is difficult as compared with the front-end including only electronic and optical elements as elements influencing the high-speed operation.
The second reason is that the cost of the disk storage system having a large number of disk drives is increased when high-speed interfaces are mounted for all of the disk drives even if operation of the disk drives is made fast.
The first conventional technique has a problem that the performance of the disk storage system is not improved due to detachment of the throughputs of the front-end and the back-end even if the data transfer rate per channel of the channel adapter is improved.
Further, it is considered that a large number of low-speed ports are provided in the disk adapter in order to improve the throughput of the back-end, although the increased ports in the disk adapter complicates control.
In the second conventional technique, switches can be provided between the disk adapter and the disk array to thereby increase the number of ports for increased disks, although there is a problem that the data transfer rate per channel is limited to that of the disk array and accordingly the throughput between the disk adapter and the disk array becomes the neck of performance.
The third conventional technique is a technique capable of reducing influence due to the waiting time caused by rotation of the disk but has a problem that detachment between the front-end and the back-end cannot be reduced.